Temperature and Interconnect Aware Unified Physical and High Level Synthesis

Temperature and Interconnect Aware Unified Physical and High Level Synthesis

Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques...

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Bibliographic Details
Main Author: Krishnan, Vyas
Format: Others
Published: Scholar Commons 2008
Subjects:
behavioral synthesis
power-aware design
thermal analysis
interconnectcentric design
stochastic interconnect estimation
layout-aware synthesis
American Studies
Arts and Humanities
Online Access:https://scholarcommons.usf.edu/etd/347
https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1346&context=etd

Internet

https://scholarcommons.usf.edu/etd/347
https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1346&context=etd

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