Cache design for low power and yield enhancement
One of the major limiters to computer systems and systems on chip (SOC) designs is accessing the main memory, which is typically two orders of magnitude slower than the processor. To bridge this gap, modern processors already devote more than half of the on-chip transistors to the last-level cache....
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| Format: | Others |
| Language: | English |
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2012
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| Online Access: | http://hdl.handle.net/2152/17884 |