BIST methodology for low-cost parametric timing measurement of high-speed source synchronous interfaces

BIST methodology for low-cost parametric timing measurement of high-speed source synchronous interfaces

With the scaling of technology nodes, the speed performance of microprocessors has rapidly improved but the scaling of off-chip input/output (I/O) bandwidth is limited by physical pin resources and interconnect technologies. In order to reduce the performance gaps, new interface techniques have emer...

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Bibliographic Details
Main Author: Kim, Hyun Jin, doctor of electrical and computer engineering
Format: Others
Language:en_US
Published: 2013
Subjects:
BIST
Timing test
Memory interfaces
Source synchronous
ATE
Online Access:http://hdl.handle.net/2152/19455

Internet

http://hdl.handle.net/2152/19455

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