Performance and energy efficiency via an adaptive MorphCore architecture

Performance and energy efficiency via an adaptive MorphCore architecture

The level of Thread-Level Parallelism (TLP), Instruction-Level Parallelism (ILP), and Memory-Level Parallelism (MLP) varies across programs and across program phases. Hence, every program requires different underlying core microarchitecture resources for high performance and/or energy efficiency. Cu...

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Bibliographic Details
Main Author: Khubaib
Format: Others
Language:en
Published: 2014
Subjects:
Computer architecture
Microprocessor
Thread-level parallelism
Instruction-level parallelism
Memory-level parallelism
Adaptive microprocessor
Energy efficiency
High performance
Power efficiency
Chip-multiprocessor
Heterogeneous computing
Online Access:http://hdl.handle.net/2152/25092

Internet

http://hdl.handle.net/2152/25092

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