Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors
Throughput processors such as GPUs continue to provide higher peak arithmetic capability. Designing a high throughput memory system to keep the computational units busy is very challenging. Future throughput processors must continue to exploit data locality and utilize the on-chip and off-chip resou...
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| Format: | Others |
| Language: | en |
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2014
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| Online Access: | http://hdl.handle.net/2152/25098 |