Layout optimization algorithms vor VLSI design and manufacturing
As the feature size of the transistor shrinks into nanometer scale, it becomes a grand challenge for semiconductor manufacturers to achieve good manufacturability of integrated circuits cost-effectively. In this dissertation, we aim at layout optimization algorithms from both manufacturing and desig...
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| Format: | Others |
| Language: | English |
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2008
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| Online Access: | http://hdl.handle.net/2152/3362 |