Analysis techniques for nanometer digital integrated circuits

Analysis techniques for nanometer digital integrated circuits

As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full...

Full description

Bibliographic Details
Main Author: Ramalingam, Anand, 1979-
Other Authors: Pan, David Z.
Format: Others
Language:English
Published: 2008
Subjects:
Integrated circuits > Very large scale integration > Design and construction
Transistors > Power supply
Integrated circuits > Very large scale integration > Thermal conductivity
Online Access:http://hdl.handle.net/2152/3661

Internet

http://hdl.handle.net/2152/3661

Similar Items