Statistical algorithms for circuit synthesis under process variation and high defect density
As the technology scales, there is a need to develop design and optimization algorithms under various scenarios of uncertainties. These uncertainties are introduced by process variation and impact both delay and leakage. For future technologies at the end of CMOS scaling, not only process variation...
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| Format: | Others |
| Language: | English |
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2008
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| Online Access: | http://hdl.handle.net/2152/3690 |