An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs
Extracting high-performance from Chip Multiprocessors (CMPs) requires that the application be parallelized i.e., divided into threads which execute concurrently on multiple cores. To save programmer effort, difficult to parallelize program portions are often left as serial. We show that common seria...
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| Format: | Others |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2010-05-1407 |