A BIST circuit for random jitter measurement
Jitter is a dominant factor contributing to a high bit error rate (BER) in high speed I/O circuitry, and it aggravates the quality of a clock signal from a phase-locked loop (PLL), subsequently impacting a given timing budget. The recent proliferation of systems-on-a-chip (SoCs) with help of technol...
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| Format: | Others |
| Language: | English |
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2012
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2012-05-5513 |