Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies
As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In t...
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| Language: | en |
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VANDERBILT
2012
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| Online Access: | http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ |