Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies
As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In t...
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ndltd-VANDERBILT-oai-VANDERBILTETD-etd-03262012-1311282013-01-08T17:16:55Z Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies Kiddie, Bradley Thomas Electrical Engineering As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In this work, several combinational circuits are selected and simulated, taking into account gate library and layout information, in order to characterize the effects of particle strikes which upset single nodes as well as multiple, physically adjacent nodes. It is shown that traditional reliability tests which simulate a single fault are not sufficient multiple faults stemming from a single strike occur and are more complex. However, multiple faults do not always translate to additional errors in the output logical reconvergence limits the effect of faults within a circuit. In order to properly understand reliability in circuit design, analysis of multiple faults should be taken into account. William H. Robinson Bharat L. Bhuva VANDERBILT 2012-03-26 text application/pdf http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ en unrestricted I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Vanderbilt University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. |
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en |
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Electrical Engineering |
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Electrical Engineering Kiddie, Bradley Thomas Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
description |
As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In this work, several combinational circuits are selected and simulated, taking into account gate library and layout information, in order to characterize the effects of particle strikes which upset single nodes as well as multiple, physically adjacent nodes. It is shown that traditional reliability tests which simulate a single fault are not sufficient multiple faults stemming from a single strike occur and are more complex. However, multiple faults do not always translate to additional errors in the output logical reconvergence limits the effect of faults within a circuit. In order to properly understand reliability in circuit design, analysis of multiple faults should be taken into account. |
author2 |
William H. Robinson |
author_facet |
William H. Robinson Kiddie, Bradley Thomas |
author |
Kiddie, Bradley Thomas |
author_sort |
Kiddie, Bradley Thomas |
title |
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
title_short |
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
title_full |
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
title_fullStr |
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
title_full_unstemmed |
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies |
title_sort |
layout-based fault injection for combinational logic in nanometer technologies |
publisher |
VANDERBILT |
publishDate |
2012 |
url |
http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ |
work_keys_str_mv |
AT kiddiebradleythomas layoutbasedfaultinjectionforcombinationallogicinnanometertechnologies |
_version_ |
1716570519715708928 |