Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology
Single-event upsets and errors are of growing concern as technology scales toward smaller transistor sizes. While smaller transistors allow for greater on-chip integration, this comes with the penalties of reduced supply voltage overhead and low drive currents compared to larger technologies. These...
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| Format: | Others |
| Language: | en |
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VANDERBILT
2011
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| Online Access: | http://etd.library.vanderbilt.edu/available/etd-04082011-122316/ |