Design Verification for Sequential Systems at Various Abstraction Levels
With the ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The most critical limitations o...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Published: |
Virginia Tech
2014
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10919/26053 http://scholar.lib.vt.edu/theses/available/etd-01282005-102938/ |