Static Learning for Problems in VLSI Test and Verification
Static learning in the form of logic implications captures Boolean relationships between various gates in a circuit. In the past, logic implications have been applied in several areas of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault diagnosi...
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Virginia Tech
2014
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Online Access: | http://hdl.handle.net/10919/28099 http://scholar.lib.vt.edu/theses/available/etd-06222005-151535/ |