Static Learning for Problems in VLSI Test and Verification

Static Learning for Problems in VLSI Test and Verification

Static learning in the form of logic implications captures Boolean relationships between various gates in a circuit. In the past, logic implications have been applied in several areas of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault diagnosi...

Full description

Bibliographic Details
Main Author: Syal, Manan
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
Untestable Faults
Logic Implications
Equivalence checking
ATPG
Online Access:http://hdl.handle.net/10919/28099
http://scholar.lib.vt.edu/theses/available/etd-06222005-151535/

Internet

http://hdl.handle.net/10919/28099
http://scholar.lib.vt.edu/theses/available/etd-06222005-151535/

Similar Items