Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not al...

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Bibliographic Details
Main Author: Iskander, Yousef Shafik
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
partial reconfiguration
reconfigurable computing
FPGA
development
debug
design validation
Online Access:http://hdl.handle.net/10919/28716
http://scholar.lib.vt.edu/theses/available/etd-08182012-001148/

Internet

http://hdl.handle.net/10919/28716
http://scholar.lib.vt.edu/theses/available/etd-08182012-001148/

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