Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers

Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers

Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test have gained more importance and 70 % of the design expenditure in on validation processes. Electronic Design Automatio...

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Bibliographic Details
Main Author: Misra, Supratik Kumar
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
Directed Acyclic Graph
Partial Scan Design
Pattern Debugger
Implication Graphs
Online Access:http://hdl.handle.net/10919/31153
http://scholar.lib.vt.edu/theses/available/etd-02062012-153606/

Internet

http://hdl.handle.net/10919/31153
http://scholar.lib.vt.edu/theses/available/etd-02062012-153606/

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