Balancing Performance, Area, and Power in an On-Chip Network
Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution....
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/34137 http://scholar.lib.vt.edu/theses/available/etd-07242003-134147/ |