ATPG based Preimage Computation: Efficient Search Space Pruning using ZBDD
Preimage Computation is a fundamental step in Formal Verification of VLSI designs. Conventional OBDD-based methods for Formal Verification suffer from spatial explosion, since large designs can blow up in terms of memory. On the other hand, SAT/ATPG based methods are less demanding on memory. Bu...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/34218 http://scholar.lib.vt.edu/theses/available/etd-07282003-144744/ |