Automatic verification of VHDL models

Automatic verification of VHDL models

<p>Verification of a model describing a hardware system is very important for modeling and simulation purposes. It is necessary to ensure that the model accurately describes the hardware system. A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has be...

Full description

Bibliographic Details
Main Author: Ardeishar, Raghu
Other Authors: Electrical Engineering
Format: Others
Language:en
Published: Virginia Tech 2014
Subjects:
LD5655.V855 1990.A736
Integrated circuits > Models > Quality control
VHDL (Computer hardware description language)
Online Access:http://hdl.handle.net/10919/41343
http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/

Internet

http://hdl.handle.net/10919/41343
http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/

Similar Items