On the generation of test patterns for combinational circuits
In this thesis, methods of identification of redundant faults and test pattern compaction are presented. The aim of the research is to improve an existing test pattern generator ATALANTA by incorporating methods for identification of redundant faults and test compaction. The faults are modeled as st...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/41915 http://scholar.lib.vt.edu/theses/available/etd-04072009-040517/ |