Susceptibility evaluation of combational logic in VLSI circuits
A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because o...
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ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-422212021-05-22T05:27:18Z Susceptibility evaluation of combational logic in VLSI circuits Modi, Manish Harsukh Electrical Engineering LD5655.V855 1990.M624 Integrated circuits -- Large scale integration A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern. This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop. Master of Science 2014-03-14T21:34:29Z 2014-03-14T21:34:29Z 1990 2009-04-25 2009-04-25 2009-04-25 Thesis Text etd-04252009-040716 http://hdl.handle.net/10919/42221 http://scholar.lib.vt.edu/theses/available/etd-04252009-040716/ en OCLC# 22336838 LD5655.V855_1990.M624.pdf In Copyright http://rightsstatements.org/vocab/InC/1.0/ ix, 84 leaves BTD application/pdf application/pdf Virginia Tech |
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LD5655.V855 1990.M624 Integrated circuits -- Large scale integration |
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LD5655.V855 1990.M624 Integrated circuits -- Large scale integration Modi, Manish Harsukh Susceptibility evaluation of combational logic in VLSI circuits |
description |
A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern.
This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop. === Master of Science |
author2 |
Electrical Engineering |
author_facet |
Electrical Engineering Modi, Manish Harsukh |
author |
Modi, Manish Harsukh |
author_sort |
Modi, Manish Harsukh |
title |
Susceptibility evaluation of combational logic in VLSI circuits |
title_short |
Susceptibility evaluation of combational logic in VLSI circuits |
title_full |
Susceptibility evaluation of combational logic in VLSI circuits |
title_fullStr |
Susceptibility evaluation of combational logic in VLSI circuits |
title_full_unstemmed |
Susceptibility evaluation of combational logic in VLSI circuits |
title_sort |
susceptibility evaluation of combational logic in vlsi circuits |
publisher |
Virginia Tech |
publishDate |
2014 |
url |
http://hdl.handle.net/10919/42221 http://scholar.lib.vt.edu/theses/available/etd-04252009-040716/ |
work_keys_str_mv |
AT modimanishharsukh susceptibilityevaluationofcombationallogicinvlsicircuits |
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