Intelligent circuit recognition for VLSI layout verification
The ability to extract higher level information from a circuit netlist is useful for VLSI layout verification. An extracted gate level description may be used as input to a gate level simulator for analysis or alternatively may be used as input to a rule-based expert system that performs verificatio...
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| Format: | Dissertation |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/42309 http://scholar.lib.vt.edu/theses/available/etd-04272010-020102/ |