Automatic back annotation of timing into VHDL behavioral models
<p>This thesis presents a design system that significantly speeds up development of VHDL behavioral models with back annotated timing. The behavioral model is developed using the CAD tool called Modeler's Assistant by inputting the model in the form of a Process Model Graph. Then using th...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/43012 http://scholar.lib.vt.edu/theses/available/etd-06102009-063425/ |