Generation of VHDL from conceptual graphs of informal specifications
This thesis describes two ongoing projects at Virginia Tech called ASPIN and the Modeler's Assistant, but is primarily concerned with a computer program known as "The VHDL Linker." This program is an interface between the two systems and interprets conceptual graphs generated from Eng...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/43313 http://scholar.lib.vt.edu/theses/available/etd-06162009-063028/ |