Design for Testability Techniques to Optimize VLSI Test Cost

Design for Testability Techniques to Optimize VLSI Test Cost

High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test dat...

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Bibliographic Details
Main Author: Donglikar, Swapneel B.
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
Test Application Time Reduction
Test Data Volume Reduction
Random Access Scan
Design for Test
Illinois Scan
Online Access:http://hdl.handle.net/10919/43712
http://scholar.lib.vt.edu/theses/available/etd-07132009-232205/

Internet

http://hdl.handle.net/10919/43712
http://scholar.lib.vt.edu/theses/available/etd-07132009-232205/

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