Timing distribution in VHDL behavioral models
This thesis describes a new CAD tool, TIMESPEC, developed for solving the timing distribution problem of allocating realistic delays to the internal primitives of a digital device. The inconsistencies in the manufacturer's specifications are also detected and corrected. Therefore, TIMESPEC enab...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/45137 http://scholar.lib.vt.edu/theses/available/etd-10102009-020318/ |