Communication Synthesis for MIMO Decoder Matrices
The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom hardware design language and communication synthesis. The framework is designed to optimize performance with matrix-type mathematical operations. The l...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/51149 http://scholar.lib.vt.edu/theses/available/etd-08172011-195854/ |