Branch Guided Metrics for Functional and Gate-level Testing
With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the techniques used to validate these designs have to constantly improve. Since most of...
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Virginia Tech
2015
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| Online Access: | http://hdl.handle.net/10919/51661 |