Sequential logic design using counters as memory elements
This thesis is concerned with the use of memory function devices in place of binary storage devices in sequential machines. In particular, various counters are considered as memory elements. Design limitations and design procedures for each type of counter are determined, with emphasis placed on UP/...
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| Format: | Others |
| Language: | en_US |
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Virginia Polytechnic Institute and State University
2016
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| Online Access: | http://hdl.handle.net/10919/64704 |