Extracting Parallelism from Legacy Sequential Code Using Transactional Memory

Extracting Parallelism from Legacy Sequential Code Using Transactional Memory

Increasing the number of processors has become the mainstream for the modern chip design approaches. However, most applications are designed or written for single core processors; so they do not benefit from the numerous underlying computation resources. Moreover, there exists a large base of legacy...

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Bibliographic Details
Main Author: Saad Ibrahim, Mohamed Mohamed
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2016
Subjects:
Transaction Memory
Automatic Parallelization
Low-Level Virtual Machine
Optimistic Concurrency
Speculative Execution
Legacy Systems
Age Commitment Order
Low-Level TM Semantics
TM Friendly Semantics
Online Access:http://hdl.handle.net/10919/71861

Internet

http://hdl.handle.net/10919/71861

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