Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking

Integrated circuit design has progressed significantly over the last few decades. This increasing complexity of hardware systems poses several challenges to the digital hardware verification. Functional verification has become the most expensive and time-consuming task in the overall product develop...

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Bibliographic Details
Main Author: Goel, Neha
Other Authors: Electrical and Computer Engineering
Format: Others
Language:en_US
Published: Virginia Tech 2017
Subjects:
Online Access:http://hdl.handle.net/10919/76840
http://scholar.lib.vt.edu/theses/available/etd-08102010-204533/