Recognition of logic blocks in CMOS circuits
A Prolog based approach towards the recognition of logic functional blocks in CMOS circuits is described in this thesis. A transistor level description of the circuit is assumed to be available. Predefined gates and logic blocks are extracted from such a description. This recognition procedure is a...
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| Format: | Others |
| Language: | en |
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Virginia Polytechnic Institute and State University
2017
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| Online Access: | http://hdl.handle.net/10919/80044 |