An automatic test generation method for chip-level circuit descriptions
An automatic method generates tests for circuits described in a hardware description language (HDL). The input description is in a non-procedural subset of VHDL, with a simplified period-oriented timing model. The fault model, based on previous research, includes micro-operation and control statemen...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
Virginia Polytechnic Institute and State University
2019
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10919/91158 |