High-Speed Clocking Deskewing Architecture
As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clo...
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| Format: | Others |
| Language: | en |
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2007
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| Online Access: | http://hdl.handle.net/10012/2993 |