High-Speed Clocking Deskewing Architecture
As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clo...
Main Author: | |
---|---|
Format: | Others |
Language: | en |
Published: |
2007
|
Subjects: | |
Online Access: | http://hdl.handle.net/10012/2993 |