AN OPTIMIZATION STAGE FOR AHPL COMPILER (LAYOUT).
The dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register T...
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| Language: | en |
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The University of Arizona.
1984
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| Online Access: | http://hdl.handle.net/10150/187701 |