VLSI REALIZATION OF AHPL DESCRIPTION AS SLA, PPLA, & ULA AND THEIR COMPARISONS (CAD).

VLSI REALIZATION OF AHPL DESCRIPTION AS SLA, PPLA, & ULA AND THEIR COMPARISONS (CAD).

Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-do...

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Bibliographic Details
Main Author: CHEN, DUAN-PING.
Other Authors: Hill, Frederick J.
Language:en
Published: The University of Arizona. 1984
Subjects:
Integrated circuits > Very large scale integration.
Compiling (Electronic computers)
Electronic circuit design.
Online Access:http://hdl.handle.net/10150/187879

Internet

http://hdl.handle.net/10150/187879

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