Design of Low-Floor Quasi-Cyclic IRA Codes and Their FPGA Decoders
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication sy...
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| Language: | EN |
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The University of Arizona.
2007
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| Online Access: | http://hdl.handle.net/10150/195295 |