The evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test search
In a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used...
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| Language: | en_US |
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The University of Arizona.
1988
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| Online Access: | http://hdl.handle.net/10150/276730 |