| Summary: | MBE growth of Si and SiGe allows a high degree of control over doping profiles and of strained alloy semiconductor growth. The structures that can be formed as a result have many potential applications for new solid state physics studies and for commercial device exploitation. However, the electrical material quality of MBE grown Si and SiGe is a function of many complex, interrelated processes and has not been extensively studied. In this work, the objectives have been to study the electrical quality of as-grown Si as a function of growth temperature and to investigate the material requirements for high mobilities (at low temperatures) in SiGe channel 2D hole gases. The former has been achieved by room temperature measurements of the generation lifetime using low temperature oxides, and the latter by parallel transport measurements at temperatures of 3K to 20K. For the first time, generation lifetimes, τg, have been measured by an MOS capacitance transient technique where all post growth processing temperatures have been below the growth temperature, Ts. These lifetimes are believed to reflect as-grown Si quality. Values of τg in Si, grown in a V80 MBE system, were found to be ~200 ns for Ts in the range 600 to 800 C. This study was limited by transient effects (that are believed to result from oxide breakdown) and no Ts dependence could be confirmed. A further study of Si grown in a V90S system revealed a complex, but repeatable, dependence of τg on Ts, with a minimum of τg=10 ns at mid-range Ts (~600 C). At high and low Ts, values of τg=12 μs were measured, as compared to values of tg X10 μs in control substrates. Importantly, post growth annealing has indicated that the Ts dependence is a not a thermal effect, i.e. it is growth related. It has been necessary to develop some techniques for device processing in order to preserve the integrity of MBE structures. Some of these techniques were applied to the processing of MBE grown pn diodes, and values of rg measured by current- and capacitance-voltage methods. These values vary greatly, ranging from 1 ns to 10 μs from epilayer to epilayer and also varied by up to an order of magnitude across an epilayer. Values of tg obtained from control substrates were also low and inconsistent; therefore, this is likely to be due to the alteration of material quality during processing. The lifetime - Ts dependence is reconcilable with the as-grown results, but provides no confirmation due to the processing induced effects. The only high temperature process used was a 1000 C, 15 second implantation activation anneal, which was assessed by the MOS technique, and shown not to alter material quality. All previous studies on SiGe channel 2D hole gases had reported relatively low mobilities, which were thought to be limited by alloy scattering. The material quality studies on this system, described here, have resulted in a maximum low temperature mobility greater than twice that previously reported for these structures. At the start of this study, mobilities were found to be limited by Cu contamination in the SiGe channel. The Cu was observed to redistribute in the structure as a result of a growth interruption and higher mobilities were obtained. Post growth annealing studies have indicated that this is a growth related effect. Modifications made to the growth technology significantly reduced the Cu concentration and further increased the mobilities. The 4K 2D hole gas mobility is shown to increase with increasing growth temperature up to 640 C, which has been associated with a reduction in interface charge scattering and, again, post growth annealing has indicated that this is associated with a growth related process. By further increasing growth temperature to 850 C, a maximum mobility of ~9000 cm2V-1s-1 was obtained. At higher growth temperatures, mobilities degraded. Experiments, in which the SiGe channel width and 2D carrier concentration were varied, have indicated that the mobility, at high growth temperatures, is limited by both interface charge and long range ripple at the upper SiGe/Si interface, which can be described in terms of interface roughness scattering.
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