Ultrashallow junctions for strain-engineered NMOS devices
CMOS scaling is rapidly reaching physical limits, forcing the industry to consider alternative routes to realise performance improvements. Strain-engineering is one such option and is already widely exploited in order to improve charge transport in the device channel. Almost every leading chipmaker...
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University of Surrey
2008
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.493239 |