Data Reuse and Parallelism in Hardware Compilation
This thesis presents a methodology to automatically determine a data memory organisation at compiletime, suitable to exploit data reuse and loop-level parallelization, in order to achieve high performanceand low power design for data-dominated applications. Moore?s Law has enabled more and more hete...
| Main Author: | |
|---|---|
| Other Authors: | |
| Published: |
Imperial College London
2008
|
| Subjects: | |
| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506018 |