The filling of submicron vias with thermally pulsed copper
In the latest 180 nm node semiconductor devices the connections between different levels of circuitry are increasingly made through copper-filled submicron barrier-coated vias formed in the insulating layers separating the wiring levels. Filling high aspect ratio vias with copper is at present accom...
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ndltd-bl.uk-oai-ethos.bl.uk-5985702015-03-20T05:48:11ZThe filling of submicron vias with thermally pulsed copperDobson, C. D.2002In the latest 180 nm node semiconductor devices the connections between different levels of circuitry are increasingly made through copper-filled submicron barrier-coated vias formed in the insulating layers separating the wiring levels. Filling high aspect ratio vias with copper is at present accomplished by electrochemical deposition which may not be extendable to the 100 nm devices planned for the year 2005. A novel copper via filling process, patented by Trikon Technologies Inc., utilises high isostatic pressures and focused laser pulse heating to extrude the copper into the vias without subjecting the device carrying semiconductor layers to unduly high temperatures. The purpose of the research reported in this dissertation was to establish the viability of the thermal pulse high pressure (TPFF) process. Three TPFF samples were studied, mainly with focused ion beam milling and imaging, utilising techniques which were developed to produce the maximum sample information on the via filling mechanisms operating during the TPFF process. It was established that TPFF filling does occur but involves the melting of the copper layers and is greatly assisted by the surface tension of the liquid copper in the barrier lined the vias. Limitations were identified in the thermal pulsing equipment which would need to be addressed if the process is to be developed successfully. The FIB images revealed little information regarding process temperatures and these were investigated with aid of a simple computer simulation. The software was verified using via filling and dimensional data extracted from the FIB results. Good correlation was found, within the experimental errors, between software model and FIB results. The model was the used to establish the optimum operating conditions for filling barrier-coated vias with diameters as small as 100 nm.621.3University of Cambridgehttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598570Electronic Thesis or Dissertation |
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621.3 Dobson, C. D. The filling of submicron vias with thermally pulsed copper |
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In the latest 180 nm node semiconductor devices the connections between different levels of circuitry are increasingly made through copper-filled submicron barrier-coated vias formed in the insulating layers separating the wiring levels. Filling high aspect ratio vias with copper is at present accomplished by electrochemical deposition which may not be extendable to the 100 nm devices planned for the year 2005. A novel copper via filling process, patented by Trikon Technologies Inc., utilises high isostatic pressures and focused laser pulse heating to extrude the copper into the vias without subjecting the device carrying semiconductor layers to unduly high temperatures. The purpose of the research reported in this dissertation was to establish the viability of the thermal pulse high pressure (TPFF) process. Three TPFF samples were studied, mainly with focused ion beam milling and imaging, utilising techniques which were developed to produce the maximum sample information on the via filling mechanisms operating during the TPFF process. It was established that TPFF filling does occur but involves the melting of the copper layers and is greatly assisted by the surface tension of the liquid copper in the barrier lined the vias. Limitations were identified in the thermal pulsing equipment which would need to be addressed if the process is to be developed successfully. The FIB images revealed little information regarding process temperatures and these were investigated with aid of a simple computer simulation. The software was verified using via filling and dimensional data extracted from the FIB results. Good correlation was found, within the experimental errors, between software model and FIB results. The model was the used to establish the optimum operating conditions for filling barrier-coated vias with diameters as small as 100 nm. |
author |
Dobson, C. D. |
author_facet |
Dobson, C. D. |
author_sort |
Dobson, C. D. |
title |
The filling of submicron vias with thermally pulsed copper |
title_short |
The filling of submicron vias with thermally pulsed copper |
title_full |
The filling of submicron vias with thermally pulsed copper |
title_fullStr |
The filling of submicron vias with thermally pulsed copper |
title_full_unstemmed |
The filling of submicron vias with thermally pulsed copper |
title_sort |
filling of submicron vias with thermally pulsed copper |
publisher |
University of Cambridge |
publishDate |
2002 |
url |
http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598570 |
work_keys_str_mv |
AT dobsoncd thefillingofsubmicronviaswiththermallypulsedcopper AT dobsoncd fillingofsubmicronviaswiththermallypulsedcopper |
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