Turbo decoder VLSI implementations for multi-standards wireless communication systems
This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo d...
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University of Edinburgh
2006
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.652056 |