Sheet resistance and electrical linewidth test structures for semiconductor process characterisation

The thesis first examines the use of the cross-bridge electrical linewidth structure to measure the sheet resistance and critical dimensions of copper damascene interconnect. This was achieved through computer simulation of current flow in the structures and served to highlight the effects of the da...

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Main Author: Smith, Stewart
Published: University of Edinburgh 2002
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Online Access:http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.662146
id ndltd-bl.uk-oai-ethos.bl.uk-662146
record_format oai_dc
spelling ndltd-bl.uk-oai-ethos.bl.uk-6621462015-12-03T03:33:38ZSheet resistance and electrical linewidth test structures for semiconductor process characterisationSmith, Stewart2002The thesis first examines the use of the cross-bridge electrical linewidth structure to measure the sheet resistance and critical dimensions of copper damascene interconnect. This was achieved through computer simulation of current flow in the structures and served to highlight the effects of the damascene process on the measurement. As a result layout design rules have been defined which minimise the errors introduced by diffusion barrier layers and dishing. Mono-crystalline silicon linewidth structures are being developed to meet the requirements for traceable metrology standards. The proposed test structures are fabricated using a wet etch process and have unusual geometries which affect their operation. Computer simulation has shown that the effects of surface interface charge and substrate biasing are the key issues that need to be addressed for accurate extraction of sheet resistance. This work has identified that increased doping of the silicon starting material reduces these effects. The use of on-mask electrical linewidth structures for alternating aperture phase shifting mask metrology has been investigated. The results compare very favourably, in terms of repeatability, with those obtained using the more common CD-SEM technique. Photolithographic simulation of submicron test structure layouts has been used to investigate the effects of applying optical proximity correction to cross-bridge linewidth structures. The effects of severe asymmetries on the Greek cross sheet resistance structure have also been examined. Finally the thesis presents examples of process characterisation using resistive test structures. In the first of these examples cross-bridge linewidth structures are used to quantify the effects of a bulk silicon, wet etch solution, which was designed to passivate metal interconnect, on the dimensions of aluminium tracks. This is followed by an investigation of the use of novel sheet resistance test structures to characterise the deposition of platinum in a focused ion beam system. The platinum sheet resistance has been characterised in terms of the main process parameters which facilitates the fabrication of resistive elements of a known value.621.3University of Edinburghhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.662146http://hdl.handle.net/1842/11416Electronic Thesis or Dissertation
collection NDLTD
sources NDLTD
topic 621.3
spellingShingle 621.3
Smith, Stewart
Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
description The thesis first examines the use of the cross-bridge electrical linewidth structure to measure the sheet resistance and critical dimensions of copper damascene interconnect. This was achieved through computer simulation of current flow in the structures and served to highlight the effects of the damascene process on the measurement. As a result layout design rules have been defined which minimise the errors introduced by diffusion barrier layers and dishing. Mono-crystalline silicon linewidth structures are being developed to meet the requirements for traceable metrology standards. The proposed test structures are fabricated using a wet etch process and have unusual geometries which affect their operation. Computer simulation has shown that the effects of surface interface charge and substrate biasing are the key issues that need to be addressed for accurate extraction of sheet resistance. This work has identified that increased doping of the silicon starting material reduces these effects. The use of on-mask electrical linewidth structures for alternating aperture phase shifting mask metrology has been investigated. The results compare very favourably, in terms of repeatability, with those obtained using the more common CD-SEM technique. Photolithographic simulation of submicron test structure layouts has been used to investigate the effects of applying optical proximity correction to cross-bridge linewidth structures. The effects of severe asymmetries on the Greek cross sheet resistance structure have also been examined. Finally the thesis presents examples of process characterisation using resistive test structures. In the first of these examples cross-bridge linewidth structures are used to quantify the effects of a bulk silicon, wet etch solution, which was designed to passivate metal interconnect, on the dimensions of aluminium tracks. This is followed by an investigation of the use of novel sheet resistance test structures to characterise the deposition of platinum in a focused ion beam system. The platinum sheet resistance has been characterised in terms of the main process parameters which facilitates the fabrication of resistive elements of a known value.
author Smith, Stewart
author_facet Smith, Stewart
author_sort Smith, Stewart
title Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
title_short Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
title_full Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
title_fullStr Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
title_full_unstemmed Sheet resistance and electrical linewidth test structures for semiconductor process characterisation
title_sort sheet resistance and electrical linewidth test structures for semiconductor process characterisation
publisher University of Edinburgh
publishDate 2002
url http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.662146
work_keys_str_mv AT smithstewart sheetresistanceandelectricallinewidthteststructuresforsemiconductorprocesscharacterisation
_version_ 1718142141533782016