Low-overhead fault-tolerant logic for field-programmable gate arrays
While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given...
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Imperial College London
2015
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.705796 |