Low-overhead fault-tolerant logic for field-programmable gate arrays

While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given...

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Main Author: Davis, James
Other Authors: Cheung, Peter
Published: Imperial College London 2015
Subjects:
Online Access:http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.705796
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spelling ndltd-bl.uk-oai-ethos.bl.uk-7057962018-07-10T03:12:41ZLow-overhead fault-tolerant logic for field-programmable gate arraysDavis, JamesCheung, Peter2015While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower area, performance and/or power consumption overheads than those incurred through the utilisation of more established, general-purpose fault tolerance methods such as modular redundancy. Field-programmable gate arrays are uniquely placed to allow further area savings to be made thanks to their dynamic reconfigurability. The majority of the technical work presented within this thesis is based upon a benchmark hardware accelerator - a matrix multiplier - that underwent several evolutions in order to detect and correct faults manifesting along its datapath at runtime. In the first instance, fault detectability in excess of 99% was achieved in return for 7.87% additional area and 45.5% extra latency. In the second, the ability to correct errors caused by those faults was added at the cost of 4.20% more area, while 50.7% of this - and 46.2% of the previously incurred latency overhead - was removed through the introduction of partial reconfiguration in the third. The fourth demonstrates further reductions in both area and performance overheads - of 16.7% and 8.27%, respectively - through systematic data width reduction by allowing errors of less than ±0.5% of the maximum output value to propagate.004.2Imperial College Londonhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.705796http://hdl.handle.net/10044/1/44382Electronic Thesis or Dissertation
collection NDLTD
sources NDLTD
topic 004.2
spellingShingle 004.2
Davis, James
Low-overhead fault-tolerant logic for field-programmable gate arrays
description While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower area, performance and/or power consumption overheads than those incurred through the utilisation of more established, general-purpose fault tolerance methods such as modular redundancy. Field-programmable gate arrays are uniquely placed to allow further area savings to be made thanks to their dynamic reconfigurability. The majority of the technical work presented within this thesis is based upon a benchmark hardware accelerator - a matrix multiplier - that underwent several evolutions in order to detect and correct faults manifesting along its datapath at runtime. In the first instance, fault detectability in excess of 99% was achieved in return for 7.87% additional area and 45.5% extra latency. In the second, the ability to correct errors caused by those faults was added at the cost of 4.20% more area, while 50.7% of this - and 46.2% of the previously incurred latency overhead - was removed through the introduction of partial reconfiguration in the third. The fourth demonstrates further reductions in both area and performance overheads - of 16.7% and 8.27%, respectively - through systematic data width reduction by allowing errors of less than ±0.5% of the maximum output value to propagate.
author2 Cheung, Peter
author_facet Cheung, Peter
Davis, James
author Davis, James
author_sort Davis, James
title Low-overhead fault-tolerant logic for field-programmable gate arrays
title_short Low-overhead fault-tolerant logic for field-programmable gate arrays
title_full Low-overhead fault-tolerant logic for field-programmable gate arrays
title_fullStr Low-overhead fault-tolerant logic for field-programmable gate arrays
title_full_unstemmed Low-overhead fault-tolerant logic for field-programmable gate arrays
title_sort low-overhead fault-tolerant logic for field-programmable gate arrays
publisher Imperial College London
publishDate 2015
url http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.705796
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