Test methodologies of VLSI circuits using scanning electron microscope.

• Other Authors: Chan, Lap-kong.
• Format: Others
• Language: English
• Published: Chinese University of Hong Kong 1994
• Subjects: Integrated circuits > Very large scale integration > Testing; Scanning electron microscopy
• Online Access: http://library.cuhk.edu.hk/record=b5888170; http://repository.lib.cuhk.edu.hk/en/item/cuhk-318218

by Chan Lap-kong. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. === Includes bibliographical references (leaves 77-80). === ABSTRACT === ACKNOWLEDGEMENTS === LIST OF FIGURES === Chapter 1. --- INTRODUCTION --- p.1 === Chapter 1.1 --- Background --- p.1 === Chapter 1.2 --- Problems in Testing VLSI Circuits --- p.3 === Chapter 1.2.1 --- Test-cost-per-gate --- p.3 === Chapter 1.2.2 --- Tester Complexity --- p.3 === Chapter 1.3 --- Tester Based on Terminals Characteristics -Automatic Testing Equipment(ATE) --- p.4 === Chapter 1.4 --- Tester Based on Terminal and Internal Characteristics --- p.6 === Chapter 1.4.1 --- Mechanical Probing Method --- p.6 === Chapter 1.4.2 --- E-beam Probing Method --- p.7 === Chapter 1.5 --- Movitation for this Research --- p.7 === Chapter 1.6 --- Outline of the Remaining Chapters --- p.9 === Chapter 2. --- E-BEAM TESTER --- p.10 === Chapter 2.1 --- State-of-art of E-Beam Tester --- p.10 === Chapter 2.2 --- An Electron-optical Column of a SEM --- p.12 === Chapter 2.3 --- Beam Rastering Methods --- p.13 === Chapter 2.4 --- Voltage Contrast Phenomenon --- p.14 === Chapter 2.5 --- Configuration of an E-Beam Test System --- p.18 === Chapter 2.6 --- Advantages of an E-beam Tester --- p.20 === Chapter 3. --- BASIC PRINCIPLES --- p.21 === Chapter 3.1 --- Single-Stuck-At Fault Model --- p.21 === Chapter 3.2 --- Observability and Controllability --- p.24 === Chapter 3.3 --- Netlist Format --- p.25 === Chapter 3.4 --- Level --- p.27 === Chapter 3.5 --- Reconvergent Fanout --- p.28 === Chapter 4. --- CONVENTIONAL TEST GENERATION --- p.29 === Chapter 4.1 --- Conventional Automatic Test Generation for ATEs --- p.29 === Chapter 4.3 --- Conventional E-Beam Test Generation --- p.31 === Chapter 5. --- TEST AND PROBE POINT GENERATION --- p.32 === Chapter 5.1 --- Wafer Stage E-beam Testing --- p.32 === Chapter 5.2 --- Critical Paths Generation --- p.33 === Chapter 5.3 --- Assumptions of the Test and Probe Point Generation Algorithm --- p.35 === Chapter 5.4 --- Rules of the Test and Probe Point Generation Algorithm --- p.36 === Chapter 5.5 --- Probe Points Selection and Reduction --- p.38 === Chapter 5.6 --- Test and Probe Point Generation Algorithm --- p.40 === Chapter 5.7 --- Propagation and Justification at Fanout Site --- p.42 === Chapter 6. --- EXAMPLES --- p.45 === Chapter 6.1 --- Example of Test and Probe Point Generation for Circuit sc2 --- p.45 === Chapter 6.2 --- Example of Test and Probe Point Generation for Circuit sfc4 --- p.53 === Chapter 7. --- CONCLUSIONS --- p.61 === Chapter 7.1 --- Summary of Results --- p.61 === Chapter 7.2 --- Further Research --- p.63 === APPENDIX === Appendix A: Algorithm to Find Reconvergent Fanouts === Appendix B: Results of Test Generation for Circuit sc1 === Appendix C: Results of Test Generation for Circuit sc3 === REFERENCES --- p.77