Optimal geometric design of VLSI interconnect networks by simulated annealing.

Optimal geometric design of VLSI interconnect networks by simulated annealing.

by Sau-yuen Wong. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. === Includes bibliographical references (leaves 77-82). === Acknowledgement --- p.i === Abstract --- p.ii === List of Tables --- p.ii === List of Figures --- p.iv === Chapter 1 --- Introduction --- p.1 === Chapter 2...

Full description

Bibliographic Details
Other Authors: Wong, Sau-yuen.
Format: Others
Language:English
Published: Chinese University of Hong Kong 1995
Subjects:
Integrated circuits > Very large scale integration > Design and construction
Simulated annealing (Mathematics)
Online Access:http://library.cuhk.edu.hk/record=b5888582
http://repository.lib.cuhk.edu.hk/en/item/cuhk-320594

Internet

http://library.cuhk.edu.hk/record=b5888582
http://repository.lib.cuhk.edu.hk/en/item/cuhk-320594

Similar Items